Large scale integrated circuits are designed by first constructing an ideal circuit represented by a schematic in which the various components in the integrated circuit are connected by “wires” that merely short the corresponding connections on the components. Typically, a designer first constructs this ideal schematic and verifies the operation of the circuit using a circuit simulator. To simplify the following discussion, this schematic representation of the integrated circuit will be referred to as the ideal circuit schematic.
The circuit that is actually manufactured can differ significantly from the circuit shown in the ideal circuit schematic because the components are not connected by ideal wires. The problems introduced by the non-ideal connections are significant at the high operating frequencies involved in RF or microwave circuits and high-speed digital circuits.
Once the designer has verified the ideal circuit, the designer lays out the components on a suitable substrate and connects the components using interconnections that consist of polygons of conductive material that are joined together and may be coupled electrically to other nearby conductors. These interconnections will be referred to as “interconnects” in the following discussion. The interconnects are not ideal conductors. Hence, the conductors in the final circuit can have electrical properties that alter the behavior of the circuit as represented by the schematic, particularly at high frequencies. That is, the components are now connected by transmission lines that have electrical characteristics that can alter the behavior of the circuit represented by the ideal circuit schematic. Hence, the device in the layout is represented by a somewhat different schematic that takes the effects of the layout into consideration. To simulate the transmission line devices, a netlist that represents this different schematic must be generated.
Dealing with the modified/altered schematics presents challenges in that the process is not easily controlled by the designer. In one class of CAD tools, the CAD tool extracts the transmission line devices using a complex rule set. The designer must synchronize the schematic from the layout which adds the new devices extracted by the device extraction engine. This can be a tedious and error-prone process. In addition, it leads to an ideal circuit that has changed, and hence, the designer's original scheme is altered in a manner that is outside the direct control of the designer.
In some systems, the layout is altered by replacing the interconnects with the extracted devices. The changes in the layout make editing the layout during the design process difficult, as the interconnects cannot be easily edited without going back to the layout before the device extraction and repeating the device extraction on the entire circuit.